MECHANICAL ENGINEERING MS THESIS DEFENSE BY MERT ÖZDEN

Title: Fabrication of Junctionless Silicon Nanowire Transistors via Mix and Match Patterning Based on Field Emission Scanning Probe Lithography

Speaker: Mert Özden

Time: August 9, 2022, 10.00

Place: Online Meeting via Zoom

Thesis Committee Members:

Prof. B. Erdem Alaca (Advisor, Koç University)

Prof. Arda D. Yalcinkaya (Boğaziçi University)

Prof. Ivo W. Rangelow (Ilmenau University of Technology)

Abstract:

Silicon nanowires (Si NWs) are one-dimensional nano-architectures that have been the promising focus of the semiconductor industry thanks to their broad application areas and various competencies. Due to their remarkable capabilities in actuating and sensing with high sensitivity in the nano-Newton range, they are highly favorable for integration into microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS). Moreover, in the last decades, they have gained a great attraction as junctionless (JL) Si NW transistors in different advanced applications such as molecular detection. In this study, to overcome the inaccessibility and difficulties of current nanofabrication technologies, field-emission scanning probe lithography (FE-SPL) was utilized as the alternative and cost-effective solution for the fabrication of JL Si NW transistors. FE-SPL, followed by cryogenic reactive-ion etching (RIE), facilitates the patterning of nanostructures and their fabrication anisotropically with a critical dimension (CD) of below 10 nm. Furthermore, proximity effects in lithography are diminished thanks to the exposure taking place through low-energy secondary electrons in FE-SPL.

In this study, a p-type highly doped silicon-on-insulator (SOI) substrate was utilized with a Si device layer (DL) thickness of 12 nm, buried oxide (BOX) layer thickness of 25 nm, and <100> surface orientation. Firstly, by employing conventional photolithography and RIE, 16 separate devices with their center regions and contact pads were formed in a four-to-four array on the DL of the SOI sample. Secondly, by performing maskless and aligned photolithography and RIE, the micro-scale features of the design were patterned and transferred into the sample. As the critical process, FE-SPL was performed to pattern Si NWs along the <110> direction and their lateral gate electrodes on a very thin photoresist (PR), AZ Barli II, with a thickness of less than 25 nm. As the final process, the etching of nano-scale features was carried out through cryogenic RIE.

The purpose of this study was to develop a novel and advanced fabrication technology, FE-SPL-based mix-and-match fabrication of JL Si NW transistors. Thanks to the feasibility of this technology, the performance parameters of JL Si NW transistors can be studied with various design possibilities in geometry and doping concentration of the NW channel. Furthermore, it is possible and promising to characterize mechanically and electronically these NWs fabricated as a junctionless resonator and an electromechanical switch by releasing the NWs with HF vapor etching of the BOX layer.